This invention relates a process for recovering disturbed, digital, optical signals and a feedback decision circuit used in such a process.
The prior art has disclosed processes for recovering severely disturbed, digital, optical signals and feedback equalizers (DFE=Decision Feedback Equalizer). For example, the publication “Equalization of Bit Distortion Induced by Polarisation Mode Dispersion”, H. Bülow, NOC 97, Antwerp 1997, p. 65 to 72 presents several possibilities of compensating dispersion using equalizers. FIG. 1 illustrates an equalizer known from the prior art. A disturbed transmitted optical signal is converted into a disturbed electrical signal 1 in an opto-electric converter. The disturbed signal is applied to a threshold decision element 2. From the output of the threshold decision element 2, the decided signal 11 is fed-back via a delay element 6. Via a multiplier the fed-back, time-delayed signal is multiplied by a parameter B1 and fed to an adder. In the prior art an analogue control process is used to obtain the parameter B1. A signal is tapped both at the input end before the threshold decision element and at the output end after the threshold decision element 2. The subtraction of these two signals yields an error signal 10 which, multiplied by the decided signal 11, yields the parameter B1. An analogue control process of this kind reacts very rapidly to changes in the optical signal. A control circuit of this kind adapts itself extremely rapidly to the circumstances of the transmission link and to disturbances caused by dispersion effects. It is advantageous to use the zero forcing algorithm, as described for example by G. KAWAS KALEH in “Zero-Forcing Decision-Feedback Equalizer for Packet Data Transmission”, Proceedings of ICC, pp. 1762–6, Geneva, May 1993.
However, on the basis of currently available semiconductor circuits, the DFE known from FIG. 1 is not capable of processing data rates above 10 GBit/s. At these high data rates the propagation time differences of the signals in the feedback loop start to become significant. Therefore alternative decision circuits are used in the prior art.
For example, German OS DE 197 47 249 describes circuits which employ parallel threshold decision elements. The splitting of the overall data rate into parallel data streams reduces the time problem in the decision circuit. A circuit as illustrated in FIG. 2 is presented as an example. Here the input signal is distributed between a plurality of decision elements 2. The decision elements each have a threshold input U1 to Un, externally controlled by a digital processor 12. The outputs of the decision elements are connected to a multiplexer 4 connected to a logic unit 5. The logic unit 5 evaluates the outputs of individual flip-flops 7 of the delay logic stage 6 in order to connect the multiplexer. A decision circuit construction of this kind solves propagation time problems at high data rates. However, in this decision circuit no difference signal between disturbed input signal 1 and fed-back signal is available for generating the error signal 10.